The PLL IP is a high speed, wide range, integer PLL with small physical area.
PLL is designed to multiply an input clock signal by an integer 40 and 50. The output is 2.5GHz with 50% duty cycle with quadrature phases.
High Speed Integer PLL IP
Overview
Key Features
- Up to 4Ghz clock output
- Wide range of multiplicand
- Small physical area
- TEST pin integrated
Block Diagram
Deliverables
- Detailed Specification and Integration guide
- LEF abstract
- GDSII layout and Mapping files
- LVS compatible netlist
- Verilog-A Model
Technical Specifications
Foundry, Node
28nm
Maturity
In Production
Availability
Immediate
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