Run Time Phase Alignment Circuit

Overview

This is a All Digital Phase Alignemnt Circuit. It uses Approximate local clock and incoming data and generates a Phase Aligned and Frequency Aligned Clock at the receiver end. This Generated Clock at the receiver end is avaliable within one clock duration.
This generated clock is aligend to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue.
This IP can operate at giga Hz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment circuitry.

Key Features

1. Sync Clock Generation in one clock duation.
2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
4. This Rx Clock can be used to -
a) Receive high speed Serial Data,
b) Convert serial to parallel,
c) Then deliver using elastic buffer of a FIFO to the Rx clock Domain for further processing.
5. This Block has further option to provide statics and configuration to phase shift further.

Benefits

Make it possible to communicate between two unaligned systems which the onchip pll or local clock generation is not accurate across. This can be due to fabrication issue, Changing distance between tx and Rx blocks. Operating frequency is too high. This make it possible to enable user to build White Rabbit Project kind of structure and does not worry much on phase alignment.

Applications

Synchronization across different nodes of high speed communications.
Like -
1. White Rabbit Project.
2. Xilinx Aurora based long distance high frequency Communication.
3. Extraction of Data with Dirty Eye Diagram Lines.
4. Optical Fiber communication
5. Wireless transmission Engines working at high speeds and have high roaming tendency and there clocks are also have large jitters.
6. Need to transmit long packed without clock computation or clock sync.
7. Multiple Chips operating on same network and have slight variations across their freq or jitter.

Deliverables

Standard Deliverables list -
1. Source Code in verilog.
2. Test Bench.
3. Simulation Scripts.
4. Synthesys scripts.
5. Documentation
6. User Guide.

Technical Specifications

Maturity

Tested On FPGA

Availability

Available

TSMC

Pre-Silicon: 28nm HPC

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