Ethernet Switch IP

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Compare 35 Ethernet Switch IP from 7 vendors (1 - 10)
  • TSN Ethernet Switched Endpoint Controller
    • The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-working (TSN) Ethernet networks.
    • It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.
    Block Diagram -- TSN Ethernet Switched Endpoint Controller
  • Multiport TSN Ethernet Switch
    • The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch.
    • It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br).
    Block Diagram -- Multiport TSN Ethernet Switch
  • Ethernet Synthesizable Transactor
    • Supports Full MII/RMII/SMII TX/RX functionality
    • Supports Mac control and data frames support
    • Ability to generate VLAN tagged and Priority tagged frames
    • Supports Pause frame detection and generation
    Block Diagram -- Ethernet Synthesizable Transactor
  • Ethercat Synthesizable Transactor
    • Supports ETG.1000 S(R) V1.0.3 specification
    • Supports Low Voltage Differential signaling interface
    • Supports MII, MDIO RMII and RGMII Interface as per the ISO/IEC 8802-3 specification
    • Supports RMII and RGMII Interface
    Block Diagram -- Ethercat Synthesizable Transactor
  • Ethernet 10GBase-KR Synthesizable Transactor
    • Supports 10G as per 802.3:
    • Supports XGMII
    • Supports XTBI (i.e Output of 8b/10b PCS)
    • Supports 10GBASE-KR with scrambler
    Block Diagram -- Ethernet 10GBase-KR Synthesizable Transactor
  • Ethernet XGMII Synthesizable Transactor
    • Follows XGMII specification as defined in IEEE 802.3
    • Supports Mac control and data frames support
    • Ability to generate VLAN tagged and Priority tagged frames
    • Supports Pause frame detection and generation
    Block Diagram -- Ethernet XGMII Synthesizable Transactor
  • Ethernet MII/RMII/GMII/RGMII Synthesizable Transactor
    • Supports Full MII/RMII/GMII/RGMII TX/RX functionality
    • Supports Mac control and data frames support
    • Ability to generate VLAN tagged and Priority tagged frames
    • Supports Pause frame detection and generation
    Block Diagram -- Ethernet MII/RMII/GMII/RGMII Synthesizable Transactor
  • Ethernet 50G Synthesizable Transactor
    • Supports 50GBase-KR/KR2 interfaces as per the specifications defined in IEEE 802.3ba
    • Supports 50G Speeds:
    • Supports 50GBase_KR
    • Supports 50GBase_KR2
    Block Diagram -- Ethernet 50G Synthesizable Transactor
  • Ethernet 40G Synthesizable Transactor
    • Supports 40G as per 802.3ba:
    • Supports XLGMII
    • Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4
    • Supports 40GBase-R
    Block Diagram -- Ethernet 40G Synthesizable Transactor
  • Ethernet 400G Synthesizable Transactor
    • Supports 400G as per 802.3bs:
    • Supports 400GBase_KR4
    • Supports 400GBase_KR8
    • Supports 400GBase_KR16
    Block Diagram -- Ethernet 400G Synthesizable Transactor
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