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Ethernet MAC IP

Welcome to the ultimate Ethernet MAC IP hub! Explore our vast directory of Ethernet MAC IP cores

The Ethernet MAC IP cores enable the host to communicate data using the Ethernet protocol (IEEE 802.3) at 10 or 100 Mbps speeds. These IP cores are composed of three main layers: the Media Access Controller (MAC), the MAC Transaction Layer (MTL), and the MAC DMA Controller (MDC).

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Search (284)
Compare 284 Ethernet MAC IP from 61 vendors (1 - 10)
  • Verification IP for Ethernet
    • Avery TSN Ethernet Verification IP provides a complete simulation-based func tional verification solution for core-level and SoC-level verification, including MAC and PHY models, protocol checking, and optional compliance test suite based on UNH-IOL test specifications.
    • Additional integration with ARM® Fast Model integration enables running the TSN IP’s software stack in one fully integrated testbench.
    Block Diagram -- Verification IP for Ethernet
  • Ultra-Low-Latency 10GE PHY+MAC
    • Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit 
    • Reconciliation sub-layer implementation compliant with IEEE802.3 
    • Local fault and remote fault detection and handling 
    • Frame Check Sequence (FCS) insertion and verification at line rate 
    Block Diagram -- Ultra-Low-Latency 10GE PHY+MAC
  • 25G/10G/SGMII/ 1000BASE-X PCS and MAC
    • OmegaCORE 25G/10G/SGMII/1000BASE-X PCS and MAC is the fully integrated Physical Coding Sublayer (PCS), KR FEC (IEEE Clause 74 – fire code FEC), SGMII/1000BASE-X and Media Access Controller (MAC) core for 25Gbps, 10Gbps, 2.5Gbps/1.25Gbps Ethernet applications which is complaint with IEEE 802.3 standard and SGMII specification 1.6.
    • The interface to the PMA supports a single channel Quad mode bidirectional, serial interface. The PCS sublayer supports both 64/66B encoding (10GE) and 8B10B encoding (SGMII/1000BASE-X) with an optional FEC layer function for backplane (10G-KR) application.
    Block Diagram -- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
  • Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
    • OmegaCORE 400G AX is a multi-channel, multi-rate Ethernet aggregator that supports tributaries from 10GE, 25GE, 40GE, 50GE, 100GE, 200GE and 400GE in combinations up to a maximum of 400GE.
    Block Diagram -- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
  • Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
    • OmegaCORE 800G DX is a multi-channel, multi-rate Ethernet aggregator that supports tributaries from 10GE to 800GE, utilizing 112G/s SerDes and 56G/s SerDes.
    • The supported Ethernet protocols are 10G, 25G, 40G, 50G, 100G, 200G, 400G, 800G and 10GFC, 16GFC, 32GFC, 64GFC, 128GFC, 256GFC, as well as FEC framing of FlexO-1/2/4-SR.
    Block Diagram -- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
  • 200G/400G/800G Ethernet PCS/FEC
    • OmegaCORE 200G/400G/800G Ethernet IP cores are cutting edge solutions to the 200G/400G/800G Ethernet application.
    • It supports the Physical Coding Sublayer (PCS) for 64B/66B, type 200G/400G/800GBASE-R function based on the Ethernet Technology Consortium and IEEE 802.3bs.
    Block Diagram -- 200G/400G/800G Ethernet PCS/FEC
  • 800G/400G/200G Ethernet MAC
    • OmegaCORE 200G/400G/800G Ethernet IP cores are cutting edge solutions to the 200G/400G/800G Ethernet application.
    • There are 4 MAC Cores: 200G MAC, 400G MAC, 800G or200G/400G/800G MAC.
    Block Diagram -- 800G/400G/200G Ethernet MAC
  • 50G/100G MAC/PCS/FEC
    • The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications is complaint with IEEE 802.3cd-2018 standard and Ethernet Technology Consortium 50GE standard.
    • The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer and symbol distribution.
    Block Diagram -- 50G/100G MAC/PCS/FEC
  • 10G/25G MAC PCS/FEC
    • OmegaCORE 10G/25G MAC/PCS/FEC is the fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 10G/25Gbps Ethernet applications which is complaint with IEEE 802.3by standard.
    • The interface to the PMA supports a single 10G/25Gbps bi-directional, serial interface.
    Block Diagram -- 10G/25G MAC PCS/FEC
  • 25GE/32GFC/CPRI10 PCS/FEC
    • The fully integrated PCS/FEC Layer core for 25Gbps Ethernet, FibreChannel 32GFC and CPRI10 applications is compliant with IEEE 802.3by2016 standard, ANSI Fibre Channel- Framing and Signaling (FC-FS-4/5) and Common Public Radio Interface (CPRI) Interface Specification, V7.0 (2015-10-09).
    Block Diagram -- 25GE/32GFC/CPRI10 PCS/FEC
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