IP Catalog > Interface IP Cores > Ethernet IP > Ethernet MAC IP

Ethernet MAC IP

Welcome to the ultimate Ethernet MAC IP hub! Explore our vast directory of Ethernet MAC IP cores

The Ethernet MAC IP cores enable the host to communicate data using the Ethernet protocol (IEEE 802.3) at 10 or 100 Mbps speeds. These IP cores are composed of three main layers: the Media Access Controller (MAC), the MAC Transaction Layer (MTL), and the MAC DMA Controller (MDC).

All offers in Ethernet MAC IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (296)
Compare 296 Ethernet MAC IP from 62 vendors (1 - 10)
  • 100G Ethernet Verification IP
    • The 100G Ethernet Verification IP (VIP)  offers a robust and high-performance solution for validating the critical MAC-to-PCS datapath in 100 Gigabit Ethernet systems.
    • Designed to ensure protocol compliance, the VIP facilitates the generation, transmission, reception, and monitoring of various Ethernet MAC frame types, all while adhering to IEEE 802.3ba and related standards.
    • Whether you are working on IP, subsystem, or SoC-level verification, this VIP is your go-to solution for comprehensive Ethernet testing.
    Block Diagram -- 100G Ethernet Verification IP
  • Centralised Network Configurator
    • Centralized Network Configurator or CNC is a component used in Time Sensitive Networking (TSN) networks.
    • The CNC monitors data streams while coordinating and managing network configuration.
    • The CNC is based on the stream reservation protocol (802.1 Qcc) to optimize the efficient use of network resources and provide Quality of Service (QoS).
    Block Diagram -- Centralised Network Configurator
  • Zonal Controller
    • Complete solution that integrates both hardware and software components including a TSN-capable Ethernet switch, a Root of Trust security module, and a transport protocol encapsulation system based on IEEE 1722
    Block Diagram -- Zonal Controller
  • Ethernet Controller
    • The Ethernet Controller is an ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connectivity across a broad range of embedded and enterprise applications.
    • Comcores offers controllers ranging from 10M to 800G enabling seamless integration into systems requiring Ethernet connectivity.
    Block Diagram -- Ethernet Controller
  • 10M End Station Controller
    • The 10M End Station Controller IP is a comprehensive hardware and software solution. It contains a Media Access Controller (MAC), a Time Of Day (TOD) system and an optional MACsec protection block.
    • The solution can interface with nearly any microcontroller or embedded processor system, either via SPI or AXI Memory Mapped host interface. The host interface can simultaneously transfer both transmit and receive packets, and the End Station Controller supports store and forward or cut-through packet handling.
    Block Diagram -- 10M End Station Controller
  • Quad Serial Gigabit Media Independent Interface (QSGMII)
    • QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps.
    • It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
    Block Diagram -- Quad Serial Gigabit Media Independent Interface (QSGMII)
  • Universal Serial 10GE Media Independent Interface (USXGMII)
    • The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
    • Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
    Block Diagram -- Universal Serial 10GE Media Independent Interface (USXGMII)
  • Serial Gigabit Media Independent Interface (SGMII)
    • SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MAC (Media Access Controller) to a PHY (Physical Layer Device).
    • It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
    Block Diagram -- Serial Gigabit Media Independent Interface (SGMII)
  • Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
    •  A combined silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018 and CPRI Specification V7.0 based solution
    • The IP-core supports 1G, 2.5G, 5G, 10G, and 25G Ethernet data rates as well as CPRI data rate option 1 (614.14M) to option 10 (24.33024G).
    Block Diagram -- Ethernet PCS 1G/2.5G/5G/10G/25G & CPRI 7.0
  • Ethernet PCS 800G
    • The 800G Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2020 and is compliant with Clause 170 and Clause 172 of the IEEE 802.3df specification.
    • 800G  Ethernet PCS IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 32-lane parallel interface and offers an 800GMII interface on the other side.
    Block Diagram -- Ethernet PCS 800G
×
Semiconductor IP