DDR IP for UMC
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DDR4 multiPHY - UMC 28HPC18
- Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
- Scalable architecture that supports data rates up to DDR4-2667
- Support for DIMMs
- Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
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DDR4 multiPHY in UMC (28nm)
- Low latency, small area, low power
- Compatible with JEDEC standard DDR4 up to 2667 Mbps
- Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
- Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
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LPDDR4 multiPHY V2 in UMC (28nm)
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
- Maximum data rate is process technology dependent
- Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
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Denali High-Speed DDR PHY for UMC
- LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
- I/O pads with impedance calibration logic and data retention capability
- Optional clock gating available for low-power control
- Multiple PLLs for maximum system margin
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DDR multi PHY
- ?Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
- ?Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
- ? Operating range of DC to 200MHz in Mobile DDR mode
- ? PHY Utility Block (PUBL) component
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DDR3/2 PHY
- ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
- ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
- ? Scalable performance from DDR2-667 through DDR3-1600
- ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps