DDR3/2 PHY

Overview

Key Features

• ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
• ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
• ? Scalable performance from DDR2-667 through DDR3-1600
• ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps
• ? Data path width scales in 8-bit increments
• ? Delivery of product as hardened IP components allows precise control of timing critical delay and skew paths
• ? Includes embedded PLL and DDLs necessary to meet timing specifications
• ? Multiple memory-rank support, up to four ranks
• ? DDR3 PHY-Controller interface runs at 1/4 the memory baud rate, simplifying core logic timing constraints
• ? Write leveling delay line (WLDL) to compensate address and control versus data delays of up to 1 clock cycle or 2500ps
• ? Write and read bit delay lines (BDLs) compensate per-bit delay skew of up to 600ps at fast PVT; delay resolution approximately 15ps under typical conditions
• ? Locally calibrated master and slave delay lines minimize OCV and ACLV effects, and accommodate V, T timing drift; delay resolution approximately 15ps under typical conditions
• ? At-speed loopback testing on both the address and data channels
• ? Delay line oscillator test mode
• ? MUX-scan ATPG

Deliverables

• We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Technical Specifications