LCD Controller IP for TSMC
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LCD Controller IP
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7
LCD Controller IP
for TSMC
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Display Controller - LCD 4K Digital Cinema (DCI)
- Support for following LCD Panel resolutions:
- 3840 x 2160 Quad / Ultra Full High Definition (QFHD)
- 4096 x 2160 Digital Cinema Systems (DCI)
- 2048 x 1080 Digital Cinema Systems (DCI)
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AXI Bus Display Controller
- Wide range of programmable Display Panel resolutions:
- Releases supporting baseline display requirements and releases with following
- optional display processing features:
- Color Palette RAM per layer or single Palette for integrated display image
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Display Controller - LCD / OLED Panels (AXI4 Bus)
- Wide range of programmable Display Panel resolutions:
- High-Resolution Display Panel support features by AXI4 Protocol:
- Releases supporting baseline display requirements and advanced releases with following optional display processing features:
- Overlay Windows option comes with advanced composition features:
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Customizable Display Controller with composition support
- Layer Blending
- Windowing
- Gamma Correction
- Color Keying
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Customizable Video Input Controller with color space conversion
- Configurable Input Formats
- Configurable Output Formats
- Configurable Codeword Correction
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Display Controller - LCD / OLED Panels (AHB Bus)
- Wide range of programmable Display Panel resolutions:
- Releases supporting baseline display requirements and advanced releases with following optional display processing features:
- Overlay Windows option comes with advanced composition features:
- Color Palette RAM per layer or single Palette for integrated display image
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Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)