Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)

Overview

Key Features

• Digital Cinema Initiative (DCI) formats: 
  •  2K – 2048 x 1080 / 12-bit X’Y’Z’ / 24/48 frames per second 
  •  4K – 4096 x 2160 / 12-bit X’Y’Z’ / 24 frames per second 
• Additional High Resolution support: 
  •  3840 x 2160 Quad / Ultra Full High Definition (QFHD) TFT LCD Panel 
• High-Resolution TFT LCD Panel support features by AXI Protocol: 
  •  Up to 16 overlap outstanding reads requests to the SDRAM Controller 
  •  Quality of Service (QoS) Support (AXI4) 
  •  Programmable burst lengths up to 16 beats (AXI3) & 256 beats (AXI4) 
  •  Wide AXI Master Port data width, up to 256-bits  
• Optional Features: 
  • Video / Graphics Base Screen with 2-16 Overlay Windows 
  •  αRGB Alpha Blending 
  •  Color Space Conversion with Chroma Resampler 
• Interface for 1,2, 8 Port TFT LCD Panel: 
  •  24-bit digital (8 bits/color) LVDS / CMOS  
• Interface to LVDS, DVI, HDMI, & DisplayPort Transmitters / Receivers  
• Programmable frame buffer bits-per-pixel  (bpp) color depths:  
  •   8,  10, 12 bits    YCrCb 
  •  16, 18, 24 bits    RGB 
• Color Palette RAM to reduce Frame Buffer memory storage requirements and AXI  Bus bandwidth (for lower color applications): 
  •  256 entry by 16-bit RAM, implemented as 128 entry by 32-bits 
• Programmable horizontal timing parameters: 
  •  horizontal front porch, back porch, sync width, pixels-per-line 
  •  horizontal sync polarity 
• Programmable vertical timing parameters: 
  • vertical front porch, back porch, sync width, lines-per-panel 
  •  vertical sync polarity 
• Programmable pixel clock:  
  •  pixel clock divider from 1 to 128 of Bus Clock 
  •  pixel clock polarity 
• Programmable Data Enable timing signal:  
  •  Derived from horizontal and vertical timing parameters 
  •  display enable polarity 
• AMBA AXI4 / AXI3 Interconnect:
  •  Selectable 256 / 128 / 64 AXI Master Port for DB9000AXI DMA access  of frame buffer memory for driving the display 
  •  Selectable 256 / 128 / 64 AXI or AXI4-Lite Slave Port for control & status  interface to microprocessor 
• Three memories: 
  •  N-word x 256 / 128 / 64 bit input FIFO, decoupling AXI bus & LCD panel  clock rates. Integrated with DMA controller 
  •  256-word x 24-bit Color Palette RAM 
  •  16-word output FIFO 
  •  FIFOs parameterizable in depth and width 
• Power up and down sequencing support 
• 9 sources of internal interrupts with masking control 
• Little-endian, big-endian, or Windows CE mode 
• AXI4 Bus  - Designed to AMBA AXI Protocol Specification (V2.0) 
• AXI3 Bus  - Designed to AMBA AXI Protocol Specification (V1.0) 
• Support in following Integrated Circuits: 
• o ASIC / ASSP with AXI4 / AXI3 fabric 
• o Altera or Xilinx FPGA with AXI fabric 
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states.

Benefits

• The DB9000AXI-DCI IP Core contains programmable features comparable to entry-level ASSP DTV & LCD controller chips,targeting FPGA & ASIC designs.

Block Diagram

Deliverables

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

Technical Specifications