The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an ASSP, ASIC, or FPGA, typically, the microprocessor is a ARM or MIPS processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
Display Controller - LCD / OLED Panels (AHB Bus)
Overview
Key Features
- Wide range of programmable Display Panel resolutions:
- Quarter VGA up to 1920x1080 HD, 4K, and 8K
- Releases supporting baseline display requirements and advanced releases with following optional display processing features:
- Overlay Windows
- Hardware Cursor
- Frame Buffer Compression
- Gamma Correction RAM
- Overlay Windows option comes with advanced composition features:
- Alpha Blending
- Color Space Conversion (CSC)
- 4:2:2 YCrCb with Re-sampling & CSC to RGB
- Programmable size, placement, & format
- Scaling
- Color Palette RAM per layer or single Palette for integrated display image
- Interface to parallel RGB, LVDS, HDMI, DisplayPort, MIPI, Vby1, BT.656
- Programmable 1,2,4,8 Port Display Panel interfaces
- Programmable horizontal & vertical timing parameters:
- front porch, back porch, sync width, pixels-per-line, lines-per-panel
- horizontal & vertical sync polarity
- Programmable frame buffer bits-per-pixel (bpp) color depths:
- 1, 2, 4, 8 bpp mapped through Color Palette
- 16, 18, 24 bpp non- Palette
- Dual display drive releases
- AMBA AXI / AHB / APB Interconnect:
- Selectable 256 / 128 / 64 / 32-bit AHB Master Port for DB9000AHB DMA access of frame buffer memory for driving the display
- Selectable 256 / 128 / 64 / 32-bit AHB (or APB) Slave Port for control & status interface to microprocessor
- Panel power up and down sequencing support
- 9 sources of internal interrupts with masking control
- Little-endian, big-endian, or Windows CE mode
- Linux OS driver
- Optional features provide customer with the exact features needed while saving on VLSI resources and licensing costs.
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states
Deliverables
- Verilog or VHDL RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
- Linux OS Driver
Technical Specifications
Foundry, Node
Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC, Global Foundaries
Maturity
Successful in Company SoC Demo Reference Design & Customer Implementations
Availability
Immediately
TSMC
In Production:
40nm
LP
,
45nm
GS
,
55nm
GP
Pre-Silicon: 40nm LP , 55nm GP
Silicon Proven: 40nm LP , 55nm GP
Pre-Silicon: 40nm LP , 55nm GP
Silicon Proven: 40nm LP , 55nm GP