TSMC N3P 1.8V IO Platform supporting cells

Overview

To address today’s content capacity and bandwidth requirements, JEDEC and SD Association continue to define new functionality and enhancements for embedded mass-storage flash memory (eMMC) and removable flash memory card (SD Card), targeting a range of applications.

The SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines. Optimized for power and area, the PHY IP is fully verified and configurable for easy integration into application processors. The PHY IP and the SD/eMMC Host Controller IP offer a fully verified solution that designers can use to integrate the latest embedded and removable memory functionality into their application processor, while speeding time-to-market.

Key Features

  • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
  • Fully integrated hard macro with high speed IOs and DLL/delay lines
  • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
  • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
  • Optimized for area
  • Scalable and low pin count solution
  • Ultra-low-power operation

Block Diagram

TSMC N3P 1.8V IO Platform supporting cells Block Diagram

Technical Specifications

Short description
TSMC N3P 1.8V IO Platform supporting cells
Vendor
Vendor Name
Foundry, Node
TSMC N3P 1.8V
TSMC
Pre-Silicon: 3nm
×
Semiconductor IP