Memory & Libraries IP for TSMC
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0.9V SLVS Transceiver in TSMC 22nm
- This SLVS I/O Library, implemented in TSMC 22nm with an 11P7M_5X1Z UT-AlRDL metal stack, provides a 0.9V differential transceiver optimized for low-power, high-speed operation.
- Supporting data rates up to 200 Mbps and compliant with JESD8-13 SLVS standards, the library features strong power supply rejection, integrated 100 on-die termination, and robust 2 kV HBM / 500 V CDM ESD protection.
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SLVS Transceiver in TSMC 28nm
- This 1.8V SLVS transceiver is a high-performance, low-power I/O solution optimized for TSMCs 28nm process.
- Designed with 1.8V thick oxide devices and a standard low-voltage core interface at 0.8V, this transceiver ensures robust operation across a wide temperature range (-40°C to 125°C).
- Supporting high-speed differential signaling up to 2Gbps, it delivers ex- ceptional signal integrity with low jitter and precise eye diagrams.
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1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.
- Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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1.8V Capable GPIO on Samsung Foundry 4nm FinFET
- The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
- This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic.
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LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
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LVDS Serializer IP
- The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
- The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
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MIPI D-PHY/LVDS Combo Receiver IP
- The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
- The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).
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MIPI D-PHY/LVDS Combo Transmitter IP
- The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
- In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.