Serdes IP for TSMC

Compare 6 Serdes IP for TSMC from 2 vendors (1 - 6)

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28nm

Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.116 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
5G Combo Serdes for USB/PCIe, TSMC 28HPC+, N/S orientation
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes
10G Combo Serdes for USB/PCIe/Ethernet, TSMC 28HPC+, N/S orientation
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes
Programmable Low Power SERDES on TSMC CLN28HPL
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.095 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 5.6 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
- Industry leading low power PMA macro – 56mW per lane at 8Gbps (7mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.2 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 1- tap DFE
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes