PLL IP for TSMC
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25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
- The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
- VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
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Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
- Entirely core voltage powered, needs no analog supply voltage
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
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Core Powered Wide Range Programmable Integer PLL on TSMC CLN3E
- Entirely core voltage powered, needs no analog supply voltage
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
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General-purpose & Specialized Ring PLLs + RTL-based Solutions
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Small area footprint
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Wide Range Programmable Integer PLL on TSMC CLN3E
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Small area footprint
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PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3P-CLN3X
- High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Spread Spectrum Clock Generation (SSCG) and tracking capability
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PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3E
- High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Spread Spectrum Clock Generation (SSCG) and tracking capability
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High Performance 20GHz C2C PLL on TSMC CLN3P-CLN3X
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
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High Performance 20GHz C2C PLL on TSMC CLN3E
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption