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Clock Generator PLL IP for TSMC

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Compare 11 Clock Generator PLL IP for TSMC from 3 vendors (1 - 10)
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  • 3nm
  • General-purpose & Specialized Ring PLLs + RTL-based Solutions
    • Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
    • Input & output frequency ranges greater than 1000:1
    Block Diagram -- General-purpose & Specialized Ring PLLs + RTL-based Solutions
  • Differential Clock Receiver to CMOS on TSMC CLN3P-CLN3X
    • Differential clock receiver
    • Single-ended output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • Differential Clock Receiver to CMOS on TSMC CLN3E
    • Differential clock receiver
    • Single-ended output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • Differential Clock Receiver to CML on TSMC CLN3P-CLN3X
    • Differential clock receiver
    • CML differential output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • Differential Clock Receiver to CML on TSMC CLN3E
    • Differential clock receiver
    • CML differential output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • TSMC CLN3PLVT 3nm Clock Generator PLL - 300MHz-1500MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN3PLVT 3nm Clock Generator PLL - 600MHz-3000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN3PLVT 3nm Clock Generator PLL - 1200MHz-6000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN3P 3nm Clock Generator PLL - 200MHz-1000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN3P 3nm Clock Generator PLL - 400MHz-2000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
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