Memory Controller/PHY IP for SMIC
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Memory Controller/PHY IP
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7
Memory Controller/PHY IP
for SMIC
from 4 vendors
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7)
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USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
- Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
- Backward compatible with 1.5Gbps, 3.0bps for SATA
- Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4 interface specification
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SATA 6G PHY in SMIC (40nm, 28nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
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M31 ESD I/O in TSMC 12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
- High Density Library
- Customized layout and function
- Flexible cell combination
- High ESD robustness analog cells
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DDR multi PHY
- ?Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
- ?Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
- ? Operating range of DC to 200MHz in Mobile DDR mode
- ? PHY Utility Block (PUBL) component
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DDR3/2 PHY
- ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
- ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
- ? Scalable performance from DDR2-667 through DDR3-1600
- ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps
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SATA 6G PHY
- ? 6-Gbps transmission rate through standard SATA cable
- ? Spread-spectrum clock (SSC) generation and absorption
- ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
- ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
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ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
- Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
- Power-sequence free
- Provides multi-driving-strength selection
- Provides CTT mode and LTT mode