SATA 6G PHY

Overview

The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SATA 6G applications. The SATA 6G PHY sata6g_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete SATA 6G physical layer capability for 6-Gbps operation, connecting a host or device controller to a SATA system. The SATA 6G PHY supports the SATA 6-Gbps protocol and data rate, and is backward-compatible with SATA Gen I and Gen II operating at 1.5-Gbps and 3.0-Gbps data rates.

Key Features

? 6-Gbps transmission rate through standard SATA cable
? Spread-spectrum clock (SSC) generation and absorption
? Programmable down-spread (+4,980 ppm through -4,980 ppm)
? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
? Supports 20-bit interface at 300-MHz operation for SATA 6-Gbps data rate
? Supports 20-bit interface at 150-MHz operation for SATA 3-Gbps data rate
? Supports 20-bit interface at 75-MHz operation for SATA 1.5-Gbps data rate
? Integrated PHY includes transmitter, receiver, SSC generation, PLL, digital core, and ESD
? Programmable Rx equalization
? Supports collapsing of power supplies
? Supports x1/x2 configurations
? Supports legacy Half-rate mode for power-saving
? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply
? Excellent performance margin and receiver sensitivity
? Robust PHY architecture that tolerates wide process, voltage, and temperature variations
? Low-jitter PLL technology with excellent supply isolation
? IEEE 1149.6 (JTAG) boundary scan
? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester:
? Supports 6-Gbps, 3-Gbps, and 1.5-Gbps test modes
? Advanced, built-in diagnostics including on-chip sampling scope for easy debug
? Visibility and controllability of hard macro functions through programmable registers in the design
? Overrides on all ASIC side inputs for easy debug
? Access register space through simple 16-bit parallel interface
? Access register space through JTAG port

Deliverables

We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Technical Specifications

Foundry, Node

TSMC,40; SMIC,40; GF,40; UMC,40

Maturity

Silicon Proven

Availability

Immediate

GLOBALFOUNDRIES

Silicon Proven: 40nm LP

SMIC

Silicon Proven: 40nm LL

TSMC

Silicon Proven: 40nm G , 40nm LP

UMC