Memory & Libraries IP for Samsung

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Compare 13 Memory & Libraries IP for Samsung from 9 vendors (1 - 10)
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
  • 1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
    • A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    • The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.
    Block Diagram -- 1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
  • LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
    • Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • x16 and x32 channel support
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
  • Ultra Low Power Embedded SRAM - Samsung 28FDSOI
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - Samsung 28FDSOI
  • Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
    • Process: Samsung 28nm FDSOI process
    • Supply voltage: 2.25V<=VDD25<=2.75V, 0.9V<=VDD10<=1.1V 1.62V<=VDD18<=1.98v
    • Mos device: pfet, nfet, egpfet, egnfet, rpposab
    • Operating current:VDD25<24mA
  • LVDS Driver/Buffer
    • Available as LVDS driver and buffer configurations
    • SLVS solutions
    • Combo LVDS + GPIO solutions
    • Available in Samsung 28FDS, 14LPP, 11LPP, 10LPP, 8LPP, 5LPP, 4LPPn
  • LVDS Receiver
    • 175Mbps to 1120Mbps
    • 25MHz to 160MHz
    • BIST support
    • Open/short detection
  • LVDS Transmitter
    • 56Mbps to 1120Mbps
    • 8MHz to 160MHz
    • BIST support
    • Open/short detection
  • Embedded OTP (One-Time Programmable) IP, 4Kx32 bits for 0.9V/1.8V FDS
    • Logic Embedded IP
    • Programming NeoFuse cell by using quantum tunneling mechanism
    • High yield performance
    • Small IP size
  • OTP One Time Programmable IP Samsung 90CIS
    • Small IP Size
    • High reliability
    • Radiation hardening
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