Memory & Libraries IP for Samsung

Compare 15 Memory & Libraries IP for Samsung from 9 vendors (1 - 10)

Samsung 8LPU 3.3V SD/eMMC PHY
- Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
- Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
- It includes an optional digi logic circuitry which is required for high-speed operations
- It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
- A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
- A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
- The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
Ultra Low Power Embedded SRAM - Samsung 28FDSOI
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
Samsung 5LPE 1.8V/3.3V SD/eMMC PHY AP2
- Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
- Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
- It includes an optional digi logic circuitry which is required for high-speed operations
- It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
Samsung 8LPU 1.8V/3.3V SD/eMMC PHY AP1
- Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
- Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
- It includes an optional digi logic circuitry which is required for high-speed operations
- It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
- Process: Samsung 28nm FDSOI process
- Supply voltage: 2.25V<=VDD25<=2.75V, 0.9V<=VDD10<=1.1V 1.62V<=VDD18<=1.98v
- Mos device: pfet, nfet, egpfet, egnfet, rpposab
- Operating current:VDD25<24mA
LVDS Driver/Buffer
- Available as LVDS driver and buffer configurations
- SLVS solutions
- Combo LVDS + GPIO solutions
- Available in Samsung 28FDS, 14LPP, 11LPP, 10LPP, 8LPP, 5LPP, 4LPPn
LVDS Receiver
- 175Mbps to 1120Mbps
- 25MHz to 160MHz
- BIST support
- Open/short detection
LVDS Transmitter
- 56Mbps to 1120Mbps
- 8MHz to 160MHz
- BIST support
- Open/short detection