eDP 1.5a RX PHY Samsung 14nm

Overview

Key Features

• Compliant to DisplayPort v1.4, eDP v1.4, and eDP v1.5a
• Supports data rates from Reduced Bit Rate (RBR:1.62 Gbps) to High Bit Rate 3 (HBR3: 8.1Gbps), and user configurable custom B/Ws
• Supports for eDP v1.4b features, such as PSR1 and PSR2
• Supports eDP v1.5a features, including AUX-less link training (Low Frequency Peridoc Signaling)
• Adaptive Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
• Automatic calibration of analog circuits and parametric offset cancellation
• Supports Built in Eye Open Monitor feature
• Built In Self Test (BIST), including DP Standard Training Pattern Sets (TPS1~TPS4), pseudo random bit stram generation and checkers
• Includes PCS layer for easier link interfaces (symbol aligning, 8b10b decoder, de-scrambler, and support for fail-safe auto recovery feature)
• AUX RX controller includes sync detection and fully synthesizable digital CDR
• Operating parameters can be fully configured by APB v3.0 and SPI interfaces

Benefits

• Low power consumption and small area
• Support for various lane configurations
• Automatic built-in self-test (Loopback) and checking PRBS random pattern

Block Diagram

Applications

• Mobile, Automotive, IoT, DDI, TCON, Chip-to-chip interconnect

Deliverables

• FE-Common: MODEL, TWRAP, TB, LEF. LIBERTY, IPXACT, ATPG, SIPI
• BE-Common: CIR, GDS, DRC, LVS, DFM
• DOC-Common: DataSheet, UserGuide, TestGuide, Register_setting, SupplementGuide

Technical Specifications