The ODT-DSP-DEC-43T250M-T16 is a 12-bit 250MHz Decimation filter with 43 taps in a 12/16nm CMOS process.
The 43 Tap Decimation filter reduces the output data rate (fDOUT) by a factor of 4 compared to the input data rate (fDIN) from an ADC.
Programmable coefficients allow customization of the filter characteristics for various application needs.
The filter is designed with programmable gain/attenuation settings for the output. Filter area is optimized by reducing the number of multipliers. Filter has bypass mode option where DIN is directly passed to DOUT.
12-bit 250MHz Decimation filter with 43 taps
Overview
Key Features
- Programmable Coefficients
- Programmable gain/attenuation at the output
- 4X Decimation Factor
- 12-Bit operation
Applications
- High speed data acquisition systems
- RF systems
- DSP applications
Deliverables
- Datasheet
- Hard Macro (GDSII and CDL)
- Verilog Model
- Liberty Files
- Power Spreadsheet
- Physical Abstract (LEF)
- Integration and Customer Support
Technical Specifications
Foundry, Node
TSMC 16nm
Availability
Now
TSMC
Pre-Silicon:
12nm
,
16nm
Related IPs
- 12-bit 250MHz interpolation filter with 43 taps
- Half-band Nyquist Decimation Filter
- TSMC CLN28HPC 12-bit 250MHz Current Steering DAC [2ch]
- CAN Bus Controller with Message Filter (Mailbox concept)
- Distributed Arithmetic FIR (DA-FIR) Filter Generator
- CAN Bus Controller with Message Filter (configurable)