VIP Portfolio Expands for Data-Intensive Hyperscale Data Centers, HPC, and AI/ML

By _Cadence Blog

June 20, 2024

New additions, including first-to-market VIP for PCIe 7.0, Ethernet 1600G, GDDR7, next-gen HBM, and DFI next-gen HBM, enable fast and comprehensive verification, ensuring SoCs meet specifications for the latest standards protocols

Cadence recently announced the extension of its Verification IP (VIP) portfolio to include support for new VIP for emerging high-speed interfaces critical in data-intensive domains, such as hyperscale data centers, high-performance computing (HPC), and artificial intelligence and machine learning (AI/ML). The new Cadence VIP offerings empower customers to confidently develop their next-generation SoCs and microcontrollers while ensuring compliance with the latest industry standards. The new offerings include VIP for PCI Express (PCIe) 7.0, Universal Chiplet Interconnect Express (UCIe) 1.1, Arm AMBA CHI-G, GDDR7, Ethernet 1600G, and next-gen HBM (HBM4).

Cadence VIP provide verification engineers with access to the industry's latest, super-fast, and highly tuned simulation performance protocols, interfaces, and memories, which are required to verify their SoC designs.

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence gives customers access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol and timing checks, coverage models, and integrated UVM System Verilog test suites, facilitating rapid adoption and effortless integration with all leading simulators.

Cadence VIP solutions include support for protocol-specific debug visualization and analysis, integrated with Cadence Verisium Debug. This enables co-debugging with signals, source code, and log files to reduce root cause analysis of protocol-related issues.

“As requirements evolve and demand increases for higher bandwidth and lower power in AI/ML and hyperscale applications, new protocols arrive at a faster pace to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With this set of new VIP, Cadence is offering customers solutions to ensure designs comply with standard specifications in the early stage as well as meet application-specific timing, power, and performance metrics to provide the fastest path to IP and SoC verification closure.”

The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence. Cadence offers state-of-the-art certification training courses for both beginning and advanced users, solidifying user understanding of verifying complex protocols.

Learn more about Cadence VIP solutions.