UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing

By Piotr Koziuk

February 4, 2026

Introduction

When discussing Universal Chiplet Interconnect Express (UCIe) a lot of, well deserved, focus is placed on the UCIe PHY itself with power and throughput performance, and physical aspects like bump pitch and area utilization. On top of this the second focus is the protocol, that runs over this link, the standard was designed with PCIe and CXL in mind, but a big part of the industry is leaning towards streaming protocols like JESD204 or simpler protocols like AXI of CXS.

But most people overlook the glue logic that needs to translate the Protocol data interface into the UCIe PHY data interface, allow for link establishment and as a nice to have offer extra reliability features. The standard specifies this as well in the form of UCIe D2D Adapter and this article will focus on exploring the Adapter features and capabilities. We will discuss the Interfaces, the reliability features, how flit data is mapped in different formats, multi-protocol multiplexing on a single link, link parameter negotiation as well as power management.

Protocol to PHY Bridge: the role of the UCIe D2D adapter

The UCIe D2D Adapter is the intermediate layer between the Protocol and the UCIe PHY. Towards the protocol layer it exposes one or more Flit Aware Die to Die Interfaces (FDI), this interface can handle both Streaming data as well as Flit encoded data in various formats. Towards the UCIe PHY it uses the Raw Die to Die interface (RDI).

The RDI can interface to a Physical Layer with a single module or multiple modules. When the Physical Layer is sending data to the D2D Adapter there is no backpressure mechanism and data is transferred whenever the pl_valid signal is asserted, in the opposite direction it is expected of the D2D adapter to continuously send data to the PHY as lp_valid and lp_ready do not de-assert. 

The protocol layer sends lp_data do the D2D Adapter when lp_irdy, lp_valid and pl_trdy are asserted. Here the transfer can stall due to pl_trdy de-assertion). In the opposite direction when the Adapter is sending data to the protocol layer there is no backpressure mechanism and the data is transferred whenever pl_valid is asserted.

Ensuring Reliability of data delivery in UCIe Die-to-Die Links

The D2D Adapter performs a CRC computation on the data that gives a 3-bit detection guarantee for random bit errors. It is always computed over 128 bytes of the message, and if the message is smaller, it is zero extended in the MSB for the purposes of computation. If the received CRC does not match the computed CRC, the flit is declared Invalid, and a replay must be requested. 

For link configurations not using Raw Format where the raw Bit Error Rate is higher than 1e-27, Retry must be supported in the Die-to-Die Adapter. If it is not these rates must not be advertised during Link Training. The retry mechanism is a simplified version of that found in PCIe. Selective Nak and Rx Retry buffer rules are not applicable, Explicit Sequence number rules are simplified, and the Flits and Ack/Nak Flits alternate, all 10-bit retry counters are replaced with 8-bit counters and other changes that simplify the retry scheme. 

The D2D adapter can also perform runtime link testing using parity computation to determine Link health by periodically injecting parity bits in the middle of a data stream. This mechanism if enabled allows the receiver to check and log parity errors based on the inserted parity bits.

Flit Mapping in the UCIe D2D Adapter: From Raw Streaming to High Reliability

A big part of the D2D functionality is Flit Data mapping. There are several formats defined that can be negotiated between link partners on top of Streaming data that make use of the reliability features described above. The simplest is the Raw format and if it is negotiated then the Adapter transfers data from Protocol Layer to Physical Layer without any modification 64B at a time. Raw mode can be negotiated by PCIe or CXL but it is also the path for other Protocols to move data across a UCIe even in a streaming fashion. JESD204E an upcoming streaming protocol for high-speed analog to digital converters (ADC) and digital to analog converter (DAC) data will make use of UCIe 3.0 for chiplet based converter applications. 

The 68B Flit Format is mandatory for CXL 68B Mode or PCIe Non-Flit Mode protocols and can optionally be deployed for streaming protocols. It is limited in its maximum data rate to 32 GT/s. The D2D Adapter will add to the 64B of data a 2B Flit Header prefix and a 2B suffix of CRC. The Header format will differ depending on Retry requirements. 

There are also 256B Flit formats that are based on the PCIe Base Specification for PCIe Flit Mode and also the CXL Specification for CXL 256B Flit Mode making support of PCIe and CXL straight forward. The protocol layer will be sending data in 256B Flits with some modifications to DLP Bytes that are partially filled by the protocol and partially by the adapter, since DLLPs are required to bypass the TX Retry buffer. A Latency-Optimized version of the 256B Flit Formats is also defined and the use for CXL is strongly recommended.

Explore UCIe D2D Adapter IP:

• UCIe D2D Adapter

Protocol arbitration and multiplexing: Support for UCIe Link Sharing

It is often the case where a design would benefit from sharing its PHY interface between multiple protocols, in UCIe with the D2D Adapter two options are available with the use of regular or enhanced multi_protocol_enable. When this link parameter is negotiated the regular mode allows for 2 identical protocol implementations to share the link if each requires half the bandwidth,  but with the enhanced mode it is possible to multiplex different protocols and for each to utilize up to 100% of the link bandwidth. 

A common flit format must be used between the protocol stacks, and the adapter so Raw format is not supported in enhanced multi_protocol_enable. The Adapter must advertise the maximum percentage of bandwidth that the receiver for each protocol can accept, and the transmitter must guarantee not to send consecutive flits of the same protocol stack on the link, instead it can interleave the flits with NOP Flits as needed.

Protocol and Parameter Negotiation for UCIe Links

The D2D adapter is responsible for Link Initialization which happens in 4 stages  (Reset of Flow, Side band Initialization, Main band Training and Repair, and Protocol parameter exchange) as well as Link State Management once Flit transfer starts. The sideband channel is used for sending messages advertising link capabilities. these include the data formatting either in specific Flit Format or Streaming Protocol in Raw Format, the support for Retry functionality and multiple protocol stacks and specific stack bandwidth limits. If the Adapter is part of a UCIe Retimer it will advertise the number of credits available for the retimer receive buffer. Additional Vendor Defined sideband messages are permitted to be exchanged to negotiate vendor-specific extensions. 

After completing all parameter exchanges the adapter reflects the results to the Protocol layer through the FDI interface and brings up the FDI interface. One this is complete the Flit data transfer can begin.

The role of the UCIe D2D Adapter in Power Management

Power Management states defined as mandatory in PCIe and CXL are also the responsibility of the D2D Adapter. There are signal handshakes defined on the FDI interface to supports L1 and L2 power states and the Adapter takes care of the state transitions. These states allow for global clock gating and system level flows like Package-Level Idle (C-states). Protocols other than PCIe and CXL can disable PM flows by sending PMNAK to any PM requests from a remote partner.

Conclusion

The Die-to-Die Adapter plays a central role in ensuring the link is properly established between link partners and the data transferred reliably and in an optimized high-performance structure. There is a lot of nuances to the implementation of the D2D Adapter and selecting the right feature subset for the custom project requires both standards expertise and implementation experience.

Chip Interfaces offers a production-ready UCIe D2D Adapter that supports robust reliability features, multiple flit formats, multi-protocol operation, and comprehensive link and power management. Designed for seamless integration into chiplet-based SoCs and UCIe retimer architectures, the solution helps customers accelerate development while reducing integration risk.