Revolutionizing Power Efficiency in PCIe 6.x: L0p and Flit Mode in Action

By Julien Eydoux

January 24, 2025

The latest PCIe 6.x specification brings groundbreaking advancements in power efficiency and performance optimization. In this technical demonstration, Senior Principal Application Engineer Julien Eydoux showcases two features of Rambus’ PCIe 6.x Controller: L0p mode and FLIT mode operation.

Dynamic Power Management

The demonstration reveals how L0p mode enables dynamic lane scaling without compromising performance. This innovative feature allows systems to adjust the number of active lanes based on actual bandwidth requirements while maintaining consistent data throughput. By switching from x4 to x1 configuration seamlessly, the system achieves significant power savings without the traditional overhead of link renegotiation.

Real-Time Analysis with XpressAGENT

Using the Rambus XpressAGENT debug IP, the demonstration provides a clear comparison between conventional lane width transitions and the new L0p capability. The traditional method shows multiple LTSSM intermediate steps that interrupt traffic flow and require additional software handling. In contrast, L0p transitions occur smoothly without any interruption to data transmission.

Technical Implementation

The demonstration utilizes:

• FPGA Virtex UltraScale+ implementation
• Rambus PCIe 6.x IP
• Seamless integration between rootport and endpoint
• Real-time monitoring and control capabilities

This technical showcase highlights our commitment to advancing PCIe technology while optimizing power consumption for modern computing needs. Watch the full demonstration to see how these innovations can benefit your next-generation designs.

Watch the demonstration video below to see L0p and Flit mode in action.