Can You Save 15% of you ASIC Package Cost Today? Hint: Wirebonds
In today’s competitive semiconductor space everybody is eager to reduce their ASIC production cost. Some say that dramatic redesign changes would lead to significant reduction in chip cost, for instance – using a more advanced silicon technology node to shrink the die size. But this is really a big and painful step.
In this post I will describe a very simple method which will enable you to cut 5% to 15% of your assembly cost.
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related Blogs
- 5 Easy Steps to Calculate ASIC Unit Cost
- Want 10nm Wafers? That'll Cost You
- Why You Need to Consider Energy Efficiency of Your HPC SoC Early On
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design