Can You Save 15% of you ASIC Package Cost Today? Hint: Wirebonds
In today’s competitive semiconductor space everybody is eager to reduce their ASIC production cost. Some say that dramatic redesign changes would lead to significant reduction in chip cost, for instance – using a more advanced silicon technology node to shrink the die size. But this is really a big and painful step.
In this post I will describe a very simple method which will enable you to cut 5% to 15% of your assembly cost.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- 5 Easy Steps to Calculate ASIC Unit Cost
- Want 10nm Wafers? That'll Cost You
- What you should ask for instead of just PPA
- Why You Need to Consider Energy Efficiency of Your HPC SoC Early On
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power