Trillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping System

By _Synopsys Blog

July 23, 2024

In today’s landscape of generative AI, IoT, and more, the demand for advanced RISC-V core IP is rapidly escalating. As technology becomes increasingly software-driven, the industry has shifted from developing hardware first and software second to a new paradigm where applications, particularly large language models in AI, are driving the architectural development. This shift has positioned RISC-V at the forefront due to its highly configurable instruction set architecture (ISA).

This flexibility is crucial as it allows developers to tailor the instruction set to specific software needs, optimizing execution, power consumption, and throughput. A robust ecosystem of semiconductor companies, including Synopsys and SiFive, is developing RISC-V IP cores to meet the increased demand. This ecosystem offers a range of products that enable customers to create their own RISC-V implementations, customizing the instruction set to achieve optimal performance for their specific applications. The ability to fine-tune and adapt RISC-V cores provides significant advantages in various market segments.

While AI is a major driver for RISC-V adoption, its applications extend to include general purpose processors for many different kinds of products all the way to 64-bit processors. The general-purpose processor market is highly competitive, with RISC-V IP providers going head-to-head with established players. This competition drives innovation and offers customers more choices in processor IPs, ultimately benefiting the industry as a whole.

Enter SiFive’s broad portfolio of RISC-V core IPs, from simple embedded microcontrollers all the way to high-end 64-bit application processor cores. Read on to learn more about SiFive’s portfolio, Synopsys’ HAPs prototypes, and how together they are enabling one trillion verification cycles per day.

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