The AndesCore™ D23-SE is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V IMAC, single/double precision FPU and DSP extensions, it supports the recently ratified ISA extensions such as B (bit manipulation), K (scalar cryptography), CMO (cache management operations) as well as Zce (code size reduction), plus Andes Custom Extension™ (ACE) for user-defined instructions. D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. Safety features include dual-core lockstep (DCLS) that is a real-time diagnostic using an additional processor and a comparator to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative as well as quantitative approaches with respect to hardware safety analysis, D23-SE is certified to be ASIL-B/D and used in highest safety-related applications.
Functional Safety
- AndesCore™ D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D
- D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
- Safety Mechanism: Split/Lock (ASIL-B/D); Single Core (ASIL-B)
- Three product name: D23-SE-DCLS; D23-SE-DCLS-LOCK; D23-SE-SC
