Partial Header Encryption in Integrity and Data Encryption for PCIe
October 14, 2024
Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols.
Background
Introducing PCIe's Integrity and Data Encryption Feature is an excellent resource to familiarize yourself with essential background needed to better comprehend PHE.
What happens in PHE?
PHE adds the option to encrypt the First/Last Double Word (DW) Byte Enable (BE) fields (when present) and a few bytes of the Address field.
To read the full article, click here
Related Semiconductor IP
- PCIe - PCI Express Controller
- R-Tile PCIe Hard IP
- P-Tile PCIe* Hard IP
- L/H-Tile PCIe Hard IP
- GTS PCIe Hard IP
Related Blogs
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Introducing PCIe's Integrity and Data Encryption Feature (IDE)
- Verification of Integrity and Data Encryption (IDE) for CXL Devices
- CXL 3.1: What's Next for CXL-based Memory in the Data Center
Latest Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Chip Design Industry Reaches an AI Inflection Point
- Cadence Agentic AI Reduces SoC/System Engineering Time by Months
- How AgentEngineer™ Technology Will Transform Engineering Workflows
- UALink: Powering the Future of AI Compute