Partial Header Encryption in Integrity and Data Encryption for PCIe
October 14, 2024
Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols.
Background
Introducing PCIe's Integrity and Data Encryption Feature is an excellent resource to familiarize yourself with essential background needed to better comprehend PHE.
What happens in PHE?
PHE adds the option to encrypt the First/Last Double Word (DW) Byte Enable (BE) fields (when present) and a few bytes of the Address field.
To read the full article, click here
Related Semiconductor IP
- PCIE CONTROLLER IIP
- PCIe Switch Verification IP
- PCIe Gen 6 Verification IP
- PCIe Gen 5 Verification IP
- PCIe Gen 2 Verification IP
Related Blogs
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Verification of Integrity and Data Encryption (IDE) for CXL Devices
- Introducing PCIe's Integrity and Data Encryption Feature (IDE)
- CXL 3.1: What's Next for CXL-based Memory in the Data Center