The Future of Silicon Innovation in the Chiplet Era
We are entering a golden age of silicon innovation with disruptive innovation shaping how the foundations of computing will be designed, delivered, and deployed at scale. This is an area of the computing landscape that the TechArena has invested more than a fair share of time with expert discussions on CXL and UCIe, two industry standards that aim to change the face of data center infrastructure as we’ve known it for the past quarter century. This is why I was delighted to catch up with Letizia Giuliano, Alphawave Semi’s vice president of IP and product management, at the MemCon conference in Mountain View, California.
Alphawave Semi has emerged as a leader in high speed connectivity IP and silicon, and while they were focused on their HBM solutions at MemCon, their ambitions are much broader moving into IP blocks that can extend from data center SSD delivery to optics to future chiplet designs for UCIe powered compute. Letizia is a veteran of semiconductor design having worked on the complex and innovative Ponte Vecchio solution at Intel before joining Alphawave Semi, and our conversation was insightfully reflective of a new breed of semi innovator that is focusing on delivering core capabilities really well to fuel optimal package delivery.
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Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
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