Protocol Debug for Complex SoCs
September 30, 2015
Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Accelerate Debug Productivity of Complex Serial Protocols
- Accelerate Debug Productivity of Complex Serial Protocols
- Overcoming the Protocol Debug Challenge
- Case Study: How To Use Protocol Debug Analyzer To Simplify Debug