Protocol Debug for Complex SoCs
September 30, 2015
Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related Blogs
- Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System
- Accelerate Debug Productivity of Complex Serial Protocols
- Accelerate Debug Productivity of Complex Serial Protocols
- Overcoming the Protocol Debug Challenge
Latest Blogs
- Satellite communications are no longer as secure as assumed
- Why Hardware Monitoring Needs Infrastructure, Not Just Sensors
- Why Post-Quantum Cryptography Doesn’t Replace Classical Cryptography
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
- Heterogeneous NPU Data Movement Tax: Intel's Own Slides Tell the Story