PCIe VIP: Accelerating Verification
April 17, 2015
In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the verification process.
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related Blogs
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
- 256Gb/s Ready Set Go : PCIe Gen6 Verification IP
- Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
- PCIe: Accelerating Debug
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility