256Gb/s Ready Set Go : PCIe Gen6 Verification IP
March 23, 2020
Synopsys Industry’s First PCIe Gen6 VIP availability gives industry leaders a head start advantage for the verification of PCIe Gen6 based designs and meet time-to-market requirements with predictable quality. As PCIe Gen6 is the most significant and disruptive update to PCIe specification in the last decade, it is critically important and advantageous to start verification early and leverage Synopsys PCIe Gen6 VIP to deal with increased verification complexity as well as ensure backward compatibility with the prior generations through PCIe VIP Source Code Test Suite.
To read the full article, click here
Related Semiconductor IP
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Flexible Pixel Processor Video IP
- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
- 100G MAC and PCS core
Related Blogs
- Industry's First Verification IP for PCIe 7.0
- Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping
- PCIe Ready for Datacenter Role
- PCIe Spread Spectrum Clocking (SSC) for Verification Engineers
Latest Blogs
- An Overview of CXL Mode Alternate Protocol Negotiation
- Design Approaches and Architectures of RISC-V SoCs
- From Spec to Silicon: Accelerate SoC Integration with IP-XACT
- Morgan State University (MSU) Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout
- Securing the Future of Terabit Ethernet: Introducing the Rambus Multi-Channel Engine MACsec-IP-364 (+363)