256Gb/s Ready Set Go : PCIe Gen6 Verification IP
Synopsys Industry’s First PCIe Gen6 VIP availability gives industry leaders a head start advantage for the verification of PCIe Gen6 based designs and meet time-to-market requirements with predictable quality. As PCIe Gen6 is the most significant and disruptive update to PCIe specification in the last decade, it is critically important and advantageous to start verification early and leverage Synopsys PCIe Gen6 VIP to deal with increased verification complexity as well as ensure backward compatibility with the prior generations through PCIe VIP Source Code Test Suite.
To read the full article, click here
Related Semiconductor IP
- Message filter
- SSL/TLS Offload Engine
- TCP/UDP Offload Engine
- JPEG-LS Encoder IP
- JPEG XS - Low-Latency Video
Related Blogs
- Industry's First Verification IP for PCIe 7.0
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
Latest Blogs
- What’s Your Vector? Synopsys Introduces New ARC VPX6 Digital Signal Processor
- Rambus CXL IP: A Journey from Spec to Compliance
- Alphawave Semi is in Play!
- Vision Transformers Have Already Overtaken CNNs: Here’s Why and What’s Needed for Best Performance
- Tailoring Root Of Trust Security Capabilities To Specific Customer Needs