PCIe Gen 4: It's Official, We're Compliant
September 18, 2019
Way back in April 2016, I wrote a post about Cadence IP for PCI Express (PCIe) Gen4 where we demonstrated compliance with Mellanox (now part of NVIDIA). As Mellanox's Gilad Shainer said to me when I talked to him back then:
"interoperability is the only way to prove standards compliance."
That was certainly true two years ago since the standard had not been completed. Cadence has attended all the Gen4 FYI testing from the time it got started in August 2017, and our PCIe Gen4 IP has interoperated with over a dozen other vendors without any issues.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up
- Cadence PCIe Solutions: Configurable, Compliant, and Low Power
- A Strategy to Verify an AXI/ACE Compliant Interconnect (2 of 4)
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing