PCI Express Trends and News at PCI-SIG 2016
PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara Convention Center at 28th-29th June, once again proving it’s not an event you want to miss. With PCIe 4.0 standard maturing, we’re seeing a lot of action in the market, though there are questions that have to be answered.
There were questions about PCIe 5.0, and though it will become an important project, the SIG wisely is staying focused on finishing PCIe 4.0. From the PR session we know PCIe 5.0 will be 32 GT/s, with specifications appearing in 2017.
To read the full article, click here
Related Semiconductor IP
- PCI Express PHY
- Multi-Channel Flex DMA IP Core for PCI Express
- PCIe - PCI Express Controller
- PCI Express PIPE PHY Transceiver
- Scalable Switch Intel® FPGA IP for PCI Express
Related Blogs
- Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth - Visit Cadence at PCI-SIG DevCon 2015
- The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016
- PCI Express: Delivering Needed Bandwidth for Open Compute Project
- Doubling Bandwidth in Under Two Years: PCI Express Base Specification Revision 5.0, Version 0.9 is Now Available to Members
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing