Moore's Law seen hitting big bump at 14 nm

By _EETimes Blog

January 14, 2013

A recent EE Times article covering IMEC's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase – and still carry a hefty cost premium – due to the lack of next-generation lithography." Van den Hove provided the following slide photo as an illustration:

Yet, in another EE Times article about Intel’s 22nm IEDM presentation, EE Times quotes Mark Bohr of Intel as saying: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate," The article also quotes Bohr as saying "The increase for 14-nm wafers at Intel is nowhere near that. Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14nm."

So who is right between those two giants?

Could it be that both of them are?

To read the full article, click here