How to reduce the risk when making the shift to RISC-V
In conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip
With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.
We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.
Vijay, what is the risk when making the shift to RISC-V?
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related Blogs
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- How to Design a RISC-V Space Microprocessor
- Legacy IP Providers Struggle to Solve the NPU Dilemna
- The Road to Innovation with Synopsys 224G PHY IP From Silicon to Scale: Synopsys 224G PHY Enables Next Gen Scaling Networks
Latest Blogs
- Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System
- ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
- Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
- Power, Not Area: Why Edge GPU Design Is Entering a New Era
- The On-Device LLM Revolution: Why 3B-30B Models Are Moving to the Edge