How to reduce the risk when making the shift to RISC-V
In conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip
With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.
We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.
Vijay, what is the risk when making the shift to RISC-V?
To read the full article, click here
Related Semiconductor IP
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- Low Power RISCV CPU IP
Related Blogs
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- The Shift-Left Approach to Software Development
- How Arm is making it easier to build platforms that support Confidential Computing
- How to Shift Left on Low-Power Design Verification, Early and Quickly
Latest Blogs
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility