How to Overcome NoC Validation Multiple Challenges?
NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. At the chip level, NocStudio generates a cache-coherent Network-on-Chip (NoC) allowing interconnecting the various CPU, GPU or Acceleration engines (the Cache-Coherent Clusters) with the I/O-Coherent and Noncoherent Agents by the means of Multiple Cache-Coherent Controllers. NetSpeed Gemini coherent NoC is high performance, scalable, and highly configurable for a wide range of applications and provides multiple benefits like routing and channels optimization, much easier place & route and lower power consumption.
But coherency is all about sharing and there is a complex set of protocols to make sure that sharing happens correctly. A bug in any part of the execution can bring down the complete scheme and product. In that sense, NetSpeed’s Gemini NoC is also an additional IP function which needs to be extensively verified. Let’s see how NetSpeed has addressed the verification challenges linked with this highly configurable coherency IP.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- NoC Verification IP
- NoC System IP
- Non-Coherent Network-on-Chip (NOC)
- Coherent Network-on-Chip (NOC)
Related Blogs
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
- Datapath Validation - Solving Verification Challenges in the Era of Artificial Intelligence and Mathematical Cores
- How to Get Started with Model-Based Systems Engineering
- How AI Is Enabling Digital Design Retargeting to Maximize Productivity
Latest Blogs
- From driveway to checkout: seamless indoor navigation powered by UWB
- Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System
- ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
- Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
- Power, Not Area: Why Edge GPU Design Is Entering a New Era