How to Overcome NoC Validation Multiple Challenges?
NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. At the chip level, NocStudio generates a cache-coherent Network-on-Chip (NoC) allowing interconnecting the various CPU, GPU or Acceleration engines (the Cache-Coherent Clusters) with the I/O-Coherent and Noncoherent Agents by the means of Multiple Cache-Coherent Controllers. NetSpeed Gemini coherent NoC is high performance, scalable, and highly configurable for a wide range of applications and provides multiple benefits like routing and channels optimization, much easier place & route and lower power consumption.
But coherency is all about sharing and there is a complex set of protocols to make sure that sharing happens correctly. A bug in any part of the execution can bring down the complete scheme and product. In that sense, NetSpeed’s Gemini NoC is also an additional IP function which needs to be extensively verified. Let’s see how NetSpeed has addressed the verification challenges linked with this highly configurable coherency IP.
To read the full article, click here
Related Semiconductor IP
- NoC System IP
- Non-Coherent Network-on-Chip (NOC)
- Coherent Network-on-Chip (NOC)
- High speed NoC (Network On-Chip) Interconnect IP
- Smart Network-on-Chip (NoC) IP
Related Blogs
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
- How to Maximize PCIe 6.0's Advantages with End-to-End PCIe Design Solutions
- FPGAs or ASICs - What Are Their Differences and Similarities and How to Use Them for Security?
- Datapath Validation - Solving Verification Challenges in the Era of Artificial Intelligence and Mathematical Cores
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power