Experts At The Table: How To Improve IP Quality
Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TSMC. What follows are excerpts of that conversation.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- Hyper-Bandwidth Multichannel Memory Subsystem
Related Blogs
- From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
- Experts At The Table: How To Improve IP Quality
- Measuring the complexity of processor bugs to improve testbench quality
- How to Unlock the Power of Operator Fusion to Accelerate AI
Latest Blogs
- UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172
- Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility
- Real PPA improvements from analog IC migration
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs