How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity
High-performance computing (HPC) is a hot topic these days, and for good reason. Consider the can containing your favorite soda – countless hours of simulation and engineering work using HPC systems have gone into designing streamlined cans that minimize aluminum waste. Indeed, the benefits of HPC are far-reaching, from its use in mining cryptocurrencies to drug testing, genome sequencing, creating lighter planes, researching space, running artificial intelligence (AI) workloads, and modeling climate change.
Processing massive amounts of data is driving demands for larger and more complex chips at advanced process nodes. What’s more, hyperscalers are transforming the way that data centers are designed and how computing resources are organized. To support their business imperatives of delivering ready access to multimedia resources, fast e-commerce transactions, quick search engine results, and the like, these companies are innovating with new data center architectures—namely, chiplets or multi-die SoC architectures.
In this blog post, I’ll discuss how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Additionally, I’ll also cover what’s needed to optimize these applications.
Related Semiconductor IP
- Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
- Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N5 X24, North/South (vertical) poly orientation
- Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N7 X16, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N6 X16, North/South (vertical) poly orientation
Related Blogs
- How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs
- New MIPI I3C V1.1 Standard Streamlines Peripheral Connectivity with Lower Cost and Higher Bandwidth
- How to Get High-Performance Simulation with Predictable Capacity Uplift in the Cloud
- How the CXL Standard Improves Latency in High-Performance Computing
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?