How Chip Design Was Revolutionized by AI-Enhanced Game Play
The Untold Story of How Google’s AlphaGo Inspired Synopsys Engineers to Transform Electronic Design Automation with Deep Reinforcement Learning
When Google’s AlphaGo triumphed over Go master Lee Sedol in 2016, Synopsys engineers Joe Walston, Stelios Diamantidis, and Thomas Andersen saw an opportunity to revolutionize the semiconductor industry. Inspired by AlphaGo’s use of reinforcement learning (RL), they began to work out how RL could also optimize and accelerate electronic design automation (EDA) techniques for silicon chips. Their idea was to use artificial intelligence (AI) and advanced machine learning (ML) models to take current design practices to a whole new level. And that’s exactly what they did.
Seven years later, Sassine Ghazi, president and chief operating officer at Synopsys, spoke at the Synopsys Users Group (SNUG) Silicon Valley 2023 conference championing what Walston, Diamantidis, and Anderson did as groundbreaking, noting how the now historic AlphaGo-Sedol match had become a “watershed” moment for the semiconductor history.
Ghazi was speaking as Synopsys launched the industry’s first full-suite of AI-enhanced design technology: Synopsys.ai. It’s a reinforcement learning-enhanced technology stack that has already given rise to 160 chip designs, and in doing so is stretching the limits of silicon chip and design team performance.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- Different By Design: Customized Processors Help Build Chip Differentiation
- How AI Will Change Chip Design
- How To Be A Chip CEO By Pasquale Pistorio
- Weakness In Consumer Chip Markets
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power