How Chip Design Was Revolutionized by AI-Enhanced Game Play
The Untold Story of How Google’s AlphaGo Inspired Synopsys Engineers to Transform Electronic Design Automation with Deep Reinforcement Learning
When Google’s AlphaGo triumphed over Go master Lee Sedol in 2016, Synopsys engineers Joe Walston, Stelios Diamantidis, and Thomas Andersen saw an opportunity to revolutionize the semiconductor industry. Inspired by AlphaGo’s use of reinforcement learning (RL), they began to work out how RL could also optimize and accelerate electronic design automation (EDA) techniques for silicon chips. Their idea was to use artificial intelligence (AI) and advanced machine learning (ML) models to take current design practices to a whole new level. And that’s exactly what they did.
Seven years later, Sassine Ghazi, president and chief operating officer at Synopsys, spoke at the Synopsys Users Group (SNUG) Silicon Valley 2023 conference championing what Walston, Diamantidis, and Anderson did as groundbreaking, noting how the now historic AlphaGo-Sedol match had become a “watershed” moment for the semiconductor history.
Ghazi was speaking as Synopsys launched the industry’s first full-suite of AI-enhanced design technology: Synopsys.ai. It’s a reinforcement learning-enhanced technology stack that has already given rise to 160 chip designs, and in doing so is stretching the limits of silicon chip and design team performance.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Different By Design: Customized Processors Help Build Chip Differentiation
- How AI Will Change Chip Design
- Weakness In Consumer Chip Markets
- Intel not interested by NVELO? Samsung was...
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?