Verification Panel: It's More Than the Hardware
In the first part of this panel discussion on verifcation, the experts talked about the state of verification technology and the progress that has been made. It concluded by bringing up the subject of software verification. Taking part in this discussion are: Gary Smith, chief analyst with Gary Smith EDA; Paul Martin, senior manager for debug, trace and performance modeling at ARM; Rajeev Ranjan, CTO with Jasper Design Automation; Harry Foster, chief verification scientist at Mentor Graphics; and Varesh Paruthi, senior technical staff member at IBM.
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- Software-Driven Hardware Verification
- Execute Your Hardware Verification Campaign in the Cloud - a Verification Engineer's Perspective
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- Hardware-Assisted Verification: The Real Story Behind Capacity
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing