Hardware-Assisted Verification: The Real Story Behind Capacity
While design engineers contemplate the power, performance and area calculation of an SoC design, their verification counterparts are thinking about whether the hardware emulation and prototyping platform available to them has enough capacity to complete the system-level verification task.
This is particularly true for verifying hardware functionality with complex software workloads. Here is where the concept of usable capacity is an important metric and often misunderstood—especially in the era of skyrocketing gate counts (2.5D- and 3D-IC stacking and chiplets) and massive software workloads. Verification engineers need to know, up front, that their hardware verification platform delivers required usable capacity to verify the SoC at the system level.
To verify large, complex designs like these, verification teams need a platform that can handle capacity scaling in a deterministic and repetitive way. For example, emulating 10 one-billion gate designs versus one 10-billion gates is different and poses significant scaling challenges for both the hardware and software.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related Blogs
- Synopsys CXL Protocol Verification Solutions Proven with Real World Vendor Devices at the CXL Compliance Test Event
- Portable Stimulus: The Next Big Leap In SoC Verification
- Moving the World with MIPS M8500 Real-Time Compute Solutions
- Real-Time Intelligence for Physical AI at the Edge
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol