Execute Your Hardware Verification Campaign in the Cloud - a Verification Engineer's Perspective
To deliver your IP hardware project, you will need a hardware verification campaign that systematically executes verification workloads against a comprehensive verification plan. How do you reach those goals with the shortest time, and the lowest cost, while delivering the highest possible quality? These are the long-established challenges of hardware verification.
Hardware verification engineers are familiar with a range of day-to-day challenges. Over the years, the EDA industry and engineering communities together have evolved effective verification workflows and strategies to address these challenges that enable them to deliver high-quality results within time and cost budgets. But the challenge to deliver quality-of-results (QOR) within both time-to-results (TTR) and cost-of-results (COR) targets is becoming ever harder to meet thanks to exponential complexity and chip design size growth, matched by compute and storage demands that push the successful delivery of complex products out of reach for smaller and some medium-sized hardware IP developers. The dominating cost is tied to hardware verification, with simulation being the dominant hardware verification workflow.
In this article, I’ll explore these challenges and then illustrate how a cloud-based hardware verification flow can help you manage key aspects of the process.
What are the challenges involved in a switch to the cloud as the main execution platform for these highly compute-intensive workflows? What are the key capabilities that must be supported in a cloud environment and what are the new opportunities that arise from that transition? How do you exploit those to improve QOR while reducing TTR and COR?
Let’s start by considering where hardware IP verification engineers spend most of their engineering time and effort. How productive is this and does the cloud both enable and enhance the experience?
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- Imparé Imparts Its Insights on Verification in the Cloud
- Portable Stimulus: The Next Big Leap In SoC Verification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Hidden Threat in Analog IC Migration: Why Electromigration rules can make or break your next tapeout
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing