MIPS' Aptiv: DSP Capabilities Become Pervasive
June 22, 2012
Last month's edition of InsideDSP discussed MIPS' recent three-core Aptiv product family announcement and provided detailed information on the high-end proAptiv offering. This follow-up article will cover the mid-range interAptiv and entry-level microAptiv cores. As with proAptiv, ARM is clearly in MIPS' gunsights with both of these new architectures.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related Blogs
- Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities
- Synopsys' EM5D and EM7D Processor Cores: The ARC Architecture Gains DSP Capabilities
- Case Study: Unlocking the Capabilities of Today's Complex SoCs for Vision
- Synopsys Enhances ARC Processor Core With Superscalar, DSP Capabilities
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol