Design-Lite - new model for semiconductor development: Taher Madraswala
Taher Madraswala, VP of Engineering, Open-Silicon Inc., presented the guest keynote titled ‘Moving toward Design-Lite for Innovation’ this afternoon at the ongoing CDNLive India 2010. His mission is clear, “We want our customers to find newer ways of growing their markets.”
Madraswala first dwelt on the EDA360 vision and the rise of the applications platform. He discussed Design-Lite — a new model for semiconductor development, as well as how companies should be using derivaties to extend their market reach, and the new design derivative ecosystem.
On EDA360, he said that the semiconductor product value is now shifting to applications. The shift is providing applications focused platforms. There are also evolving integration challenges in both software and IP.
He added that non-traditional semiconductor development tasks are being pushed to the ecosystem. In this regard, the ecosystem collaboration is critical for success.
To read the full article, click here
Related Semiconductor IP
- eDP 2.0 Verification IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
Related Blogs
- EDA / IP Business Model Debate: Daniel Nenni versus Aart de Geus
- The Semiconductor IDM Business Model is Dead!
- A Three-Tier Business Model for benefitting the Global Semiconductor Industry
- New Protocol (NB- IoT) Requires New DSP IP and New Business Model
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing