New Protocol (NB- IoT) Requires New DSP IP and New Business Model
If we agree on the definition of IoT as a distributed set of services based on sensing, sharing and controlling through new nodes, we realize that these nodes are a big hardware opportunity. The chip makers and IP vendors have to create innovative SoC, delivering high performance at low cost and low energy. Moreover, the new systems will have to integrate multiple sensors and stay in Always Alert mode.
The problem comes when you realize that no processor core is ideally suited for all these 3 functions: sensing, computation and communication.
Sensing is going from voice/face trigger to biometric monitoring, indoor navigation to sensor fusion, and probably many more as we can be confident about the creating power of innovators. Computation is linked with maths: Digital Signal Processing, bit manipulation, floating point, encryption, security, etc. when communications is based on protocol standards like NB-IoT, Wi-Fi Halow, GNSS, BLE or Zigbee.
Because every IoT application is different and because the above list is pretty long, no processor cores are ideally suited for all 3 functions, sensing, computing and communicate. Cadence, and more precisely Tensilica team developing the highly configurable DSP IP core, has brainstormed and realize that cost and ease of use are driving the desire for single core for IoT SoCs. The next step has been to develop the new Fusion F1 DSP core, able to compute, support sensing and communication protocols.
Related Semiconductor IP
- VeriSilicon NB-IoT Cat NB1/NB2 RF IP
- LTE NB-IOT (NB1) power optimized transceiver for cellular IoT
- Ultra-low-power LTE NB-IoT transceiver (+ PA)
- UE LTE-M (Cat-M) / NB-IoT SAW-less TRX 400MHz~2.7GHz (with integrated PA)
Related Blogs
- Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications
- Which CEVA DSP to use to Support Multimode Connectivity Requirements of IoT and M2M?
- CEVA-X1 DSP Core Targets Cellular IoT Opportunities
- Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?