DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps
March 21, 2016
Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY. Since then we have made great progress with customers, and our own silicon bring up. Most recently, the combo PHY IP is brought up in our lab and running at 2400 Mbps.
Many price sensitive consumer products continue to leverage 28nm technology for affordable high performance and low power consumption. Originally announced at Memcon 2014, and developed for TSMC 16FF+, this IP has been selected by multiple customers for their mobile and enterprise server/networking applications. Read about how that IP has been demonstrated running at 3200Mbps here.
Related Semiconductor IP
- Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
Related Blogs
- Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer Products
- HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
- See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?