Chiplet Summit: Challenges of Chiplet-Based Designs
I wrote the first post, The Chiplet Summit, from the recent Chiplet Summit in San Jose, If you have not seen that, you should probably read it first.
A leitmotiv of the conference was:
Moore's Law is dead. All we have left is packaging.
As I said in the final summary paragraph of my earlier post:
The situation today is that single-company multi-chiplet designs are shipping in volume, tentative steps are being made with some chiplets to build ecosystems of partners around them, and the dream of a chiplet store is sufficiently far off as to remain a dream for the time being.
Today, I want to look at the technical issues that will require solutions to be able to do chiplet-based designs with chiplets from multiple companies who did not pre-plan making those specific chiplets work together. The analogy is how you can buy chips from different manufacturers and put them together on a PCB and have a working system, even though the companies that designed the chips never planned that specific system.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related Blogs
- Datapath Validation - Solving Verification Challenges in the Era of Artificial Intelligence and Mathematical Cores
- The Future of Chiplet Reliability
- Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
- Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms