Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
To read the full article, click here
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related Blogs
- Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
- Overcoming USB Type-C Verification Challenges
- NAND Flash Memory - Key Element For Your Multi-Die Systems Verification - Part 1
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
Latest Blogs
- Silicon Insurance: Why eFPGA is Cheaper Than a Respin
- One Bit Error is Not Like Another: Understanding Failure Mechanisms in NVM
- Introducing CoreCollective for the next era of open collaboration for the Arm software ecosystem
- Integrating eFPGA for Hybrid Signal Processing Architectures
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity