Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
March 18, 2024
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
To read the full article, click here
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related Blogs
- Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
- Overcoming USB Type-C Verification Challenges
- NAND Flash Memory - Key Element For Your Multi-Die Systems Verification - Part 1
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
Latest Blogs
- Satellite communications are no longer as secure as assumed
- Why Hardware Monitoring Needs Infrastructure, Not Just Sensors
- Why Post-Quantum Cryptography Doesn’t Replace Classical Cryptography
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
- Heterogeneous NPU Data Movement Tax: Intel's Own Slides Tell the Story