Calligo Enables Next-Gen Computing at Scale with Synopsys Digital Design Flow
In a time when high-performance computing (HPC), big data, and artificial intelligence/machine learning (AI/ML) reign supreme, numbering systems are the talk of the town. While floating-point numbers have long been used in diverse computing environments, posits are emerging as an option with the greater precision that HPC applications demand.
CalligoTech, an Indian Silicon Valley startup focused on developing products and solutions for HPC, big data, and AI/ML, has helped pioneer the commercialization of posit arithmetic in hardware and software. Its new accelerator, TUNGA (Technology for Unum-based Next Generation Arithmetic), is the first multi-core RISC-V processor with posits. The company recently achieved successful tape-out of the processor using the Synopsys Digital Design Family and is on a path toward delivering more energy-efficient CPUs.
“As a startup, having access to a full digital design flow backed by good support was critical to our success,” said Vinay N Hebballi, chief operating officer at CalligoTech. “Synopsys answered the call on both fronts, providing foundry-proven signoff tools that helped us achieve a successful tape-out.”
To read the full article, click here
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related Blogs
- How AI Is Enabling Digital Design Retargeting to Maximize Productivity
- Can GPUs Accelerate Digital Design Implementation?
- CoreHW Develops 80GHz mmWave PLL with Synopsys RFIC Design Flow on GlobalFoundries 22FDX Technology
- Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow
Latest Blogs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
- Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
- From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained