The Rambus LPDDR4X/4 controller core is designed for use in applications
requiring high memory throughput at low power including mobile, Internet of
Things (IoT), automotive, laptop PCs, and edge networking devices.
LPDDR4X / LPDDR4 Controller
Overview
Key Features
- Maximizes bus efficiency via look-ahead command processing, bank management, and auto-precharge
- Latency minimized via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports full-rate, half-rate and quarter-rate clock operation
- Multi-mode controller support
- Full run-time configurable timing parameters and memory settings
- Supports LPDDR4X/4 data bus inversion (DBI) and data mask (DM)
- Supports self-refresh, partial array self-refresh, power down, and deep power down modes
- DFI compatible
- Full set of add-on cores available
- Can be delivered fully integrated and verified with target PHY
- Minimal ASIC gate count
- Broad range of ASIC platforms supported
- Source code available
- Customization and integration services available
Deliverables
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Technical Specifications
Foundry, Node
Any
Availability
Now
Related IPs
- SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
- LPDDR4 Controller IP
- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- LPDDR4/3, DDR4/3 Memory Controller IP
- LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
- SDRAM DDRx & LPDDR4x Hardened PHY - TSMC 12nm 12FFC,FFC+