LPDDR4 Synthesizable Transactor

Overview

LPDDR4 Synthesizable Transactor provides a smart way to verify the LPDDR4 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR4 Synthesizable Transactor is fully compliant with standard LPDDR4 Specification and provides the following features.

Key Features

Supports 100% of LPDDR4 protocol standard JESD209-4,JESD209-4A,JESD209-4B,JESD209-4C,JESD209-4D,JESD209-4X and JESD209-4Y (proposed)
Supports all the LPDDR4 commands as per the specs
Supports memory densities upto 32GB
Supports device types X8 and X16
Supports all mode registers programming
Supports all data rates as per specification
Supports both 16 and 32 programmable burst lengths
Supports all types of timing and protocol violation detection
Supports programmable read/write latency timings
Supports burst sequence
Checks for following:

Check-points include power up,initialization and power off rules
State based rules, active command rules
Read/write command rules etc
All timing violations

Supports write and read DBI
Supports write data mask and data strobe features
Supports write leveling
Supports CA training
Supports byte mode
Supports ODT(on-die termination) features
Supports ZQ calibration commands
Supports DQ calibration
Supports DQ vref training
Supports for single-ended mode
Supports power down features
Supports self refresh
Supports refresh management
Supports full-timing as well as behavioral versions in one model
On-the-fly protocol and data checking
Protocol checker fully compliant with LPDDR4 specification JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4D, JESD209-4X and JESD209-4Y(proposed)

Benefits

Compatible with testbench writing using SmartDV's VIP
All UVM sequences/testcases written with VIP can be reused
Runs in every major emulators environment
Runs in custom FPGA platforms

Block Diagram

Deliverables

Synthesiable transactors
Complete regression suite containing all the LPDDR4 testcases
Example's showing how to connect various components, and usage of Synthesizable Transactor
Detailed documentation of all DPI, class, task and function's used in verification env
Documentation also contains User's Guide and Release notes

Technical Specifications

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